MK5027 |
RFQ for MK5027 Required Field |
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| Product | Manufacturers | Pack | D/C |
| MK5027 | - | 04+ | 1 |
The SGS-THOMSON Signalling System #7 Sig nalling Link Controller (MK5027) is a VLSI semiconductor device which provides a complete link control function conforming to the 1988 CCITT version of SS7. This includes frame formatting, transparency (so called "bit-stufling"), error recovery by two types of retransmission, error monitoring, sequence number control, link status control, and FISU generation. One of the outstanding features of the MK5027 is its buffer management which includes on-chip DMA. This feature allows users to handlq multiple packets of receive and transmit data at a time. (A conventional data linkcontrol chip plus a separate DMA chip would handle data for only a single block at a time.) The MK5027 may be used with any of several popular 16 and 8 bit microprocessors, such as 68000, 6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc.
Features |
| `CMOS `FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS`SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE`COMPLETE LEVEL 2 IMPLEMENTATION `COMPATIBLE WITH 1988 CCITT, AT&T, ANSI, AND BELLCORE SIGNALLING SYSTEM NUMBER 7 LINK LEVEL PROTOCOLS`52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN COMPATIBLE WITH THE SGS-THOMSON X.25 CHIP (MK5025) AND NEARLY PIN-FORPIN COMPATIBLE WITH THE SGS-THOMSON VLANCE CHIP (MK5032)`BUFFER MANAGEMENT INCLUDES: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes.`ON CHIP DMA CONTROL WITH PROGRAMMABLE BURST LENGTH`SELECTABLE BEC OR PCR RETRANSMISSION METHODS, INCLUDING FORCED RETRANSMISSIONFOR PCR`HANDLES ALL 7 SS7 TIMERS`HANDLES ALL SS7 FRAME FORMATTING: - Zero bit insert and delete - FCS generation and detection - Frame delimiting with flags`PROGRAMMABLE MINIMUM SIGNAL UNIT`SPACING(number of flags between SU's) `HANDLES ALL SEQUENCING AND LINK CONTROL`SELECTABLE FCS OF 16 OR 32 BITS.`TESTING FACILITIES: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test`ALL INPUTS AND OUTPUTS ARE TTL COMPATIBLE`PROGRAMMABLE FOR FULL OR HALF DUPLEX OPERATION |
| Temperature under Bias |
25°C to +100 |
| Storage Temperature |
65°C to +150 |
| Voltage on Any Pin with Respect to Ground |
0.5V to VCC +0.5V |
| Power Dissipation |
0.50W |
